# Generic makefile , do NOT edit !

# !!! GNU Make needed !!!

include Makefile.in

RM    = rm -f
CC    = gcc
INC   = -I ../ -I ../vm -I ../compiler
MKDEP = -M
AR    = ld -r -o

ARCHIVE = .lib
DEPEND  = .depend

OBJ = $(shell for X in . $(TODO) ; do if [ "$$X" != . ] ; then printf "%s " "$$X.o" ; fi ; done)
SRC = $(shell for X in . $(TODO) ; do if [ "$$X" != . ] && [ -f $$X.cpp ] ; then printf "%s " "$$X.cpp" ; fi ; if [ "$$X" != . ] && [ -f $$X.c ] ; then printf "%s " "$$X.c" ; fi ; done)
ARC = $(shell for X in . $(SUBS) ; do if [ "$$X" != . ] ; then printf "%s " "$$X/$(ARCHIVE)" ; fi ; done)


all: subs $(ARCHIVE)

subs:
	@for X in . $(SUBS) ; do if [ "$$X" != . ] ; then $(MAKE) -C $$X ; fi ; done

arc: $(ARCHIVE)
$(ARCHIVE): $(DEPEND) $(OBJ) $(ARC)
	$(AR) $(ARCHIVE) $(OBJ) $(ARC)
	@chmod 755 $(ARCHIVE)

%.o: %.c
	if [ -f $*.c ]; then $(CC) $(CFLAGS) $(INC) -c $*.c -o $@; fi


%.o: %.cpp
	if [ -f $*.cpp ]; then $(CC) $(CFLAGS) $(INC) -c $*.cpp -o $@; fi



clean:
	@for X in . $(SUBS) ; do if [ "$$X" != . ] ; then $(MAKE) -C $$X clean ; fi ; done
	$(RM) $(OBJ) $(ARCHIVE) $(DEPEND)

dep: $(DEPEND)
$(DEPEND): Makefile.in
	$(CC) $(MKDEP) $(CFLAGS) $(INC) $(SRC) >$(DEPEND)

ifneq ($(wildcard $(DEPEND)),)
  include $(DEPEND)
endif
